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jackrabbit tm phoneline network phy transceiver chipset CPC6000 / cpc6100 description the CPC6000 physical layer (phy) and cpc6100 analog front end (afe) jackrabbit? phoneline network transceiver chipset provides an economically robust solution for home and small business pc users to network their computer and internet equipment together through ordinary copper telephone wires installed in their dwelling or office building. operating simultaneously with ordinary telephone service (pots) as well as anal og and xdsl modems, the jackrabbit? home phoneline network phy chipset allows consumers to easily share high speed internet services, play multi-player networked games and share peripheral equipment and files. the CPC6000 and cpc6100 jackrabbit? transceiver chipset connects directly between an ind ustry standard ethernet media access controller (mac) over an industry standard mii (media independent interface) or gpsi (general purpose se rial interface) interface and any rj11 phone jack attached to the existing internal telephone wires. the jackrabbit? chipset operates at speeds up to 10 mbps while in high speed turbo mode in addition to providing a home phone network alliance (homepna) interoperability mode with a more robust 1mbps te chnology. consisting of the 80-pin tqfp packaged CPC6000 digital phy device and the 48-pin tqfp packaged afe, the jackrabbit? chipset and available reference designs provide oems with a complete low cost home phoneline network interface card (nic) solution. features turbo mode data speed of up to 10mbps, 5mbps and 1mbps within 4.5mhz C 24.5mhz band homepna interoperability mode at 1mbps and 0.7mbps within the 4.5mhz to 9.5mhz band based upon patent and patent pending dual carrier segment modulation (dcsm)* and adaptive template demodulation (atcd)* technology robust connectivity in severely impaired networks with bridged taps and other wire impairments out of band spectral energy > -35db without external filtering superior s/n error performance C typically <10 -10 raw ber (without error correction) at an snr of 8db direct connects with up to 500 feet of category 0 to category 5 twisted pair wire low power consumption: <400mw over 1500vrms isolation with external transformer inexpensive 4 pole discrete filter provides proper termination compatible with either 3v or 5v power supplies onboard plls allowing inexpensive crystal for mac and phy clock source. polarity insensitive small 80-pin tqfp and 48-pin tqfp packaging applications home phoneline network pci nic cards home phoneline network usb nic cards and adapters home phoneline network pcmcia nic cards phoneline adapter or dongle for standard ethernet 10/100 nic cards network printers and scanners residential gateway systems set top boxes - shared entertainment xdsl modems - shared internet cable modems - shared internet voice over ip phones (web-phones) internet gaming systems remote metering video conferencing home monitoring and security systems home automation systems approvals ul1950 ul1459 fcc part 15b fcc part 68 homepna 1.0 reference design certification rev. 0a, 2/8/00
2 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary table of contents description .................................................................................................................... ............................................................................. 1 features ....................................................................................................................... ............................................................................... 1 applications ................................................................................................................... ............................................................................ 1 pending approvals .............................................................................................................. ...................................................................... 1 jackrabbit tm chipset pin desciption ......................................................................................................... ................................................. 4 CPC6000 phy pin description .................................................................................................... ........................................................... 4 cpc6100 afe pin description: ................................................................................................... ........................................................... 6 system configuration block diagrams ............................................................................................ ...................................................... 8 fig. 1 - pci bus half card system configuration ................................................................................ .................................................. 8 fig. 2 - usb port system configuration ......................................................................................... ....................................................... 8 fig. 3 C adapter/dongle system configuration ................................................................................... .................................................. 9 introduction ................................................................................................................... ......................................................................... 10 functional description ......................................................................................................... ................................................................. 10 fig. 4 - homepna 1mb/s frame structure ......................................................................................... ................................................ 11 phy core description ........................................................................................................... ................................................................... 12 overview ....................................................................................................................... ........................................................................ 12 fig. 5 C simplified CPC6000 phy block diagram .................................................................................. ............................................. 12 fig. 6 C simplified cpc6100 afe block diagram .................................................................................. ............................................. 13 mac interface .................................................................................................................. ................................................................... 13 turbo mode data transmitter .................................................................................................... ...................................................... 13 fig. 7 C turbo mode preamble ................................................................................................... ........................................................ 13 fig. 8 - post state machine transmitter logic ................................................................................. .................................................. 14 homepna interoperability (1mbps) transmitter ................................................................................... ......................................... 14 fig. 9 - homepna 1mbps transmitter logic ....................................................................................... ................................................ 14 turbo mode receive path ........................................................................................................ ........................................................... 15 fig. 10 C turbo mode receiver .................................................................................................. ......................................................... 15 homepna interoperability (1mbps) receiver ...................................................................................... ............................................ 16 fig. 11 C homepna interoperability (1mbps) pulse detector ...................................................................... ....................................... 16 interfaces ..................................................................................................................... ............................................................................ 16 mii interface .................................................................................................................. ...................................................................... 16 mii vendor specific register definitions ....................................................................................... ................................................. 17 register 0: control register ................................................................................................... ............................................................. 17 register 1: status register .................................................................................................... ............................................................. 18 register 2: phy identifier register ............................................................................................ .......................................................... 18 register 3: phy identifier register ............................................................................................ .......................................................... 18
3 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary registers 4 C 8: auto-negotiation registers .................................................................................... ................................................... 18 registers 9 & 10: 100 baset2 control and status registers ...................................................................... ......................................... 19 registers 11 to 14: reserved registers ......................................................................................... ..................................................... 19 register 15: extended status register .......................................................................................... ...................................................... 19 register 16: jackrabbit tm phy control register .......................................................................................................... ........................ 19 registers 17 C 23: unused registers ............................................................................................ ..................................................... 20 register 24: jackrabbit tm clock control register ........................................................................................................ ........................ 20 register 25: jackrabbit tm phy test register ............................................................................................................. .......................... 20 registers 26 C 32: unused registers ............................................................................................ ..................................................... 20 fig. 12 - mii interface block diagram .......................................................................................... ...................................................... 21 seven wire serial (gpsi) interface ............................................................................................. ..................................................... 21 table 1 C gpsi interface signals ............................................................................................... ......................................................... 21 serial peripheral interface .................................................................................................... ......................................................... 22 fig. 13 - gpsi and spi port interfaces ......................................................................................... ....................................................... 22 comparator (adc) interface ..................................................................................................... ........................................................ 22 dac interface .................................................................................................................. .................................................................... 23 ethernet nic dongle interface .................................................................................................. ...................................................... 23 clock options .................................................................................................................. .................................................................... 23 pins for device testing ........................................................................................................ .............................................................. 23 miscellaneous pins ............................................................................................................. ............................................................... 23 phoneline interface external components ........................................................................................ ............................................... 24 line driver .................................................................................................................... ....................................................................... 24 receive path ................................................................................................................... ...................................................................... 24 isolation ...................................................................................................................... ......................................................................... 24 transmit filter ................................................................................................................ ................................................................... 24 front end protection ........................................................................................................... ............................................................. 24 electrical characteristics ..................................................................................................... .............................................................. 25 operating conditions (CPC6000 and cpc6100) ..................................................................................... ........................................... 25 CPC6000 dc electrical characteristics .......................................................................................... ............................................... 25 CPC6000 ac electrical characteristics .......................................................................................... ............................................... 25 cpc6100 dc electrical characteristics .......................................................................................... ............................................... 26 cpc6100 ac electricalspecifications ............................................................................................ ................................................. 27 mechanical dimenions ........................................................................................................... ................................................................. 28 CPC6000 phy mechanical dimenions ............................................................................................... ................................................. 28 cpc6100 afe mechanical dimensions .............................................................................................. ................................................. 28
4 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary jackrabbit tm chipset pin description pin # name type description 1 spi_dout o spi port data out. used in gpsi mode for communication with phy. 2 test_xmit1 nc no connect. leave pin floating. for production test. 3 vcc pwr digital power pin. 3.3v +/- 10%. power to pll. 4 pll_60_lf o pin for external filter to 60mhz pll circuit. see application schematic. 5 vdd gnd ground pin for 60mhz pll circuit. 6 test_xmit10 nc no connect. leave pin floating. for production test. 7 vcc pwr digital power pin. 3.3v +/- 10%. connects to digital core. 8 vdd gnd ground pin. connects digital core to digital ground plane. 9 vdd gnd digital ground to the mii interface. 10 spi_cs i chip select strobe for the spi port. leave pin as a nc. 11 rx_d3 o receive data for mii interface. inactive in gpsi mode. 12 rx_d2 o receive data for mii interface. inactive in gpsi mode. 13 rx_d1 o receive data for mii interface. inactive in gpsi mode. 14 rx_d0 o receive data for mii interface. used as rx_d in gpsi mode. 15 crs o carrier sense for mii interface. on when tx or rx non-idle. also used in gpsi mode. 16 col o collision detect for mii interface. also used on gpsi interface. 17 md_add4 i input on power-up. sets mii physical address in mii register. 18 md_add3 i input on power-up. sets mii physical address in mii register. 19 md_add2 i input on power-up. sets mii physical address in mii register. 20 md_add1 i input on power-up. sets mii physical address in mii register. 21 md_add0 i input on power-up. sets mii physical address in mii register. 22 vcc pwr digital power pin. 3.3v +/- 10% power to internal pads. 23 vcc pwr digital power pin. 3.3v +/- 10%. for oscillator section. CPC6000 phy pin description CPC6000 phy pinout 40 21 41 20 60 1 61 80 jackrabbit tm CPC6000
5 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary pin # name type description 24 xtal2 i crystal connection. connect through 10pf cap. 25 xtal1 o crystal connection. 26 vdd gnd oscillator ground pin. connected to digital ground plane. 27 vcc pwr digital power pin. 3.3v +/- 10% power to internal pads. 28 link_act o link activation led driver. outputs 16ma. 29 rx_mode o for powering led on card. outputs hpna / turbo mode indication. 30 dac_0 o output from modulator to dac on cpc6100 afe. 31 dac_1 o output from modulator to dac on cpc6100 afe. 32 dac_2 o output from modulator to dac on cpc6100 afe. 33 dac_3 o output from modulator to dac on cpc6100 afe. 34 dac_4 o output from modulator to dac on cpc6100 afe. 35 vdd gnd connect to digital ground. return for pads. 36 vcc pwr digital power pin. 3.3v +/- 10% power to internal pads. 37 dac_clk o clock from modulator to cpc6100 afe. drives sampling rate. 38 dac_5 o output from modulator to dac on cpc6100 afe. 39 dac_6 o output from modulator to dac on cpc6100 afe. 40 dac_7 o msb output from modulator to dac on cpc6100 afe. 41 dac_scal o dac scaling pin. connects through resistor selection to afe vref pin. 42 g_comp1 i input from comparator on cpc6100 afe for phoneline network connections. 43 p_comp1 i input from comparator on cpc6100 afe for phoneline network connections. 44 n_comp1 i input from comparator on cpc6100 afe for phoneline network connections. 45 g_comp2 i input from comparator on cpc6100 afe for nic card connections. 46 p_comp2 i input from comparator on cpc6100 afe for nic card connections. 47 n_comp2 i input from comparator on cpc6100 afe for nic card connections. 48 manch_clk o clock source for comparator bank #2 sampling. 49 vcc pwr digital power pin. 3.3v +/- 10%. power to the pads. 50 vdd gnd ground connection to digital core. connect to digital ground plane. 51 vcc pwr digital power pin. 3.3v +/- 10%. power to 10baset core (endec block). 52 pll_disab i pll disable. sampled on power up, active high. has internal pull down. 53 vdd gnd ground for 80mhz pll circuit. connect to digital ground plane. 54 pll_80_lf2 i/o connection from 80mhz pll to digital ground through filter. 55 vcc pwr digital power pin. 3.3v +/- 10%. power for pll. 56 rref i connect to digital ground through a 6.19k resistor to digital ground. 57 vcc pwr digital power pin. 3.3v +/- 10%. power to the pads. 58 ck_60_mon i/o used to force 60mhz operation for testing. leave as no connect. 59 60_clk_in i/o 60mhz clock oscillator input. 60 80_clk_in i/o 80mhz clock oscillator input. 61 gpsi_en i used to enter gpsi mode after reset. must be pulled low with reset. 62 manch_n o output to nic card. capacitively coupled to transformer C positive side. 63 manch_p o output to nic card. capacitively coupled to transformer + positive side. 64 int_a o output to mac or controller to signify interrupt condition. open drain output. 65 ck_25 o 25mhz output to mac for clock to mac chip. 66 vdd gnd connect to digital ground. return for pads. 67 rst i reset. will reset the device and all registers return to default values. 68 tx_clk o transmit clock for mii interface. 25% of data rate. also used for gpsi.
6 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary pin # name type description 69 tx_en i transmit enable for mii interface. also used for gpsi interface. 70 tx_er i transmit error for mii interface. valid only when tx_en also set. 71 tx_d3 i transmit data for mii interface. inactive in gpsi mode. 72 tx_d2 i transmit data for mii interface. inactive in gpsi mode. 73 tx_d1 i transmit data for mii interface. inactive in gpsi mode. 74 tx_d0 i transmit data for mii interface. used as tx_d in gpsi mode. 75 rx_clk o receive data clock for mii interface. also used for gpsi interface. 76 rx_dv o receive data valid for mii interface. started at packet deliminator. 77 rx_er o receive error for mii interface. any error detected by phy. 78 vcc pwr power connection to digital core. 3.3v +/- 10%. 79 spi_clk/mdc i/o mgt data clock for mii interface. also, used for spi port in gpsi mode. 80 spi_di/mdio i/o mgt data in/out for mii interface. also, used for spi port in gpsi mode for spi data input. muxed with spi_dout to emulate mdio for software compatibility. cpc6100 afe pin description cpc6100 afe pinout pin # name type description 1 nc nc no connect. leave floating. 2 dac_7 i input from CPC6000 modulator to afe dac C transmit to twisted pair. (msb) 3 dac_6 i input from CPC6000 modulator to afe dac C transmit to twisted pair. 4 dac_5 i input from CPC6000 modulator to afe dac C transmit to twisted pair. 5 vdd pwr digital power pin. 3.3v +/- 10%. 6 vssa gnd ground. connect to analog ground plane. 7 dac_clk i input from modulator chip. drives sampling rate. 8 dac_4 i digital input from CPC6000 modulator to dac C transmit to line. 9 dac_3 i digital input from CPC6000 modulator to dac C transmit to line. 10 dac_2 i digital input from CPC6000 modulator to dac C transmit to line. 11 vdd pwr digital power pin. 3.3v +/- 10%. 24 25 13 12 36 37 48 1 jackrabbit tm cpc6100
7 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary pin # name type description 12 vssa gnd ground. connect to analog ground plane. 13 dac_1 i input from CPC6000 modulator to afe dac C transmit to twisted pair. 14 dac_0 i input from CPC6000 modulator to afe dac C transmit to twisted pair. (lsb) 15 vssa gnd ground. connect to analog plane. 16 vssa gnd ground. connect to analog plane. 17 ref_g1 i ground reference to phoneline network signal input from twisted pair wire. 18 ref_p1 i positive reference to phoneline network signal input from twisted pair wire. 19 sig_in1 i signal input from anti alias filter from the twisted pair input. 20 ref_n1 i negative reference to phoneline network signal input from twisted pair wire. 21 ref_g2 i ground reference for manchester signal from nic card. 22 ref_p2 i positive reference to manchester signal from nic card. 23 sig_in2 i manchester signal input from nic card. 24 ref_n2 i negative reference to manchester signal from nic card. 25 nc nc no connect. leave as float. 26 vdd pwr digital power pin. 3.3v +/- 10%. 27 vdd pwr digital power pin. 3.3v +/- 10%. 28 nc nc no connect. leave as float. 29 nc nc no connect. leave as float. 30 vss gnd ground connection. 31 comp2_clk i clock for manchester comparators. connect to manch_clk on digital chip. 32 n_comp2 o output to CPC6000 modulator. manchester receive data from nic card. 33 p_comp2 o output to CPC6000 modulator. manchester receive data from nic card. 34 g_comp2 o output to CPC6000 modulator. manchester receive data from nic card. 35 n_comp1 o output to CPC6000 modulator. phoneline network receive data. 36 nc nc no connect. leave floating. 37 p_comp1 o output to CPC6000 modulator. phoneline network receive data. 38 g_comp1 o output to CPC6000 modulator. phoneline network receive data. 39 vdd pwr digital power pin. 3.3v +/- 10%. 40 vssa gnd analog ground pin. connect to analog ground plane. 41 vssd gnd digital ground. connect to digital ground plane. 42 r_bias i sets reference in dac. connected through 6.19k resistor. 43 vdda pwr power to analog section. 3.3v +/- 10%. 44 rb/dd i connect to vdd. sets internal bias point. 45 i_neg i negative current output source. 10ma max. to twisted pair line. 46 vref i sets reference for dac. connect through 0.1uf cap to ground. 47 i-pos o positive current source output. 10ma max, or 1volt output. 48 vdd pwr digital power pin. 3.3v +/- 10% at current source.
8 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary system configuration block diagrams figure 1. pci bus half card system configuration figure 2. usb port system configuration netbios emulators, sockets, app. software lan protocols (tcp/ip, udp, etc.) ndis lan media type ndis intermediate layer ndis media type (upper part of wrapper) ndis driver (modified 802.3 driver) ndis media type (hw abstraction layer) host software stack p c i b u s mii standard 10/100 ieee 802.3 mac CPC6000 phy 80 tqfp cpc6100 afe 48 tqfp discretes (transformer, driver, filters) jackrabbit tm rj11 phone wire netbios emulators, sockets, app. software lan protocols (tcp/ip, udp, etc.) ndis lan media type ndis intermediate layer ndis media type (upper part of wrapper) ndis driver (modified 802.3 driver) ndis media type (hw abstraction layer) host software stack u s b p o r t gpsi standard 10/100 ieee 802.3 mac-usb adapter CPC6000 phy 80 tqfp cpc6100 afe 48 tqfp discretes (transformer, driver, filters) gpio spi spi jackrabbit tm rj11 phone wire
9 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary figure 3. adapter/dongle system configuration netbios emulators, sockets, app. software lan protocols (tcp/ip, udp, etc.) ndis lan media type ndis intermediate layer ndis media type (upper part of wrapper) ndis driver (modified 802.3 driver) ndis media type (hw abstraction layer) host software stack p c i b u s standard 10/100 ieee 802.3 mac CPC6000 phy 80 tqfp cpc6100 afe 48 qfp discretes (transformer, driver, filters) standard 10/100 ieee 802.3 phy rj45 rj11 "dongle" jackrabbit tm phone wire
10 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary introduction the personal computer has become a powerful platform in the home for work, communication, education, and entertainment. the internet has exploded into an essential means of information access. just as there is a critical need for high-speed connections to information and broadband entertainment outside the home, there is a growing need for this type of networking access inside the home as more and more homes have multiple pcs and users. until recently, however, local area networks have not penetrated the home because of the poor quality of the in-home phone wiring installation and the high cost of running dedicated wiring in a finished home. in-home phone wires are frequently run to jacks that either have no telephone attached or have a phone that is not of high quality. often wires have simply been cut leaving a tap, or bridged tap, that does not affect voice communications but causes major problems for high speed data services. bridged taps cause major problems in data transmission because they will actually reflect the transmitted signal and cause destructive interference with the data transmission as the time delay in the reflected signal is summed with the signal currently being sent. in addition, most communication techniques have been constructed for an environment where there are many subscribers and precious copper resources. this historically resulted in modulation techniques such as (quaternary amplitude modulation) qam, which attempts to squeeze as many bits into as small a spectrum as was possible. 16, 32, 64, 128, and even 256 qam have been proposed in the home telephone environment. this truly is a waste of resources C measured by processor cycles, silicon gates, or even system cost as qam attempts to rebuild the original waveform through equalization, modulation, error correction and a host of other methods. the many taps and single customer residential wiring actually presents the exact inverse of central office plant which contains few taps and many subscribers. to solve the problems encountered with phoneline networking, the jackrabbit tm chipset uses a much less complex modulation technique. the general consideration is to send a known data pattern into the channel, and to model the channel with all of its corruptive influences in a template that can be adaptive on a packet by packet basis. the resulting pattern is then correlated with future data transmissions within that same packet with a patented technique called adaptive template correlation. this results in a receiver that is little more than a simple state machine with much less demand on the analog to digital conversion process. to further this robust process, a patented dual carrier segment modulation* technique is used to create a bitstream from symbols. the carriers used are frequency diverse such that a reflection reacting destructively with one carrier constructively acts with the other carrier. therefore, the technology used in the jackrabbit tm chipset does not require restoration of the carrier envelope through equalization and long training sequences but adapts within 24 data bits at the beginning of each packet. functional description the CPC6000 and cpc6100 chipset perform the same functions that a standard ethernet 10/100mbs phy performs with the exception that category 5 ethernet wiring is not required since the jackrabbit tm chipset operates over standard twisted pair telephone wire. from the perspective of a standard ethernet mac, the same protocols are used to communicate with other ethernet cards. the only modification to any osi layer above the phy is a slight modification to the ndis driver to allow for automatic speed negotiation during data transmission. this is a required change for home phone networking systems due to the fact that communication at a set speed (10/100) is not viable in an environment with rapidly changing characteristics. at the phy layer, an ethernet frame is stripped of its preamble and another preamble is appended to the frame. at the other end of the transmission channel, the reverse process is performed. because all of the transmissions occur in turbo mode at 4.5mhz - 24.5mhz or in the homepna interoperability mode band of 4.5mhz - 9.5mhz, all jackrabbit tm phoneline lan communications are frequency division multiplexed with normal pots, v.90 modem, isdn, and adsl services for coexistence inside the home. the jackrabbit tm chipset and available reference design is interoperable with the homepna 1mbps specification (version 1.1) using robust dcsm* and atcd* mod/demod technology. the homepna interoperability mode of operation allows transmission at 1mb/s and 0.7mb/s depending on the channel impairment characteristics, and provides a common platform upon which all current and future homepna certified home phoneline lan cards can communicate with each other. in addition, the jackrabbit tm chipset and available reference design will automatically turbo up to communicate at the highest speed allowed by the channel (10mbps, 5mbps or 1mbps) when communicating to another node on the network incorporating jackrabbit tm technology. when the chipset is powered up, software on the host system (ndis driver) will poll all other nodes on the network. this is done exhaustively so that all nodes on the network will build a speed look up table that will combine each cards ethernet address with the fastest speed that each node can be communicated with over the existing channel. this polling technique is performed at regular programmable multiples of 2-second intervals so that if the channel
11 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary characteristics change, communications with each node will continue to be optimized for its maximum performance capabilities. the home or small office network is dynamic and significant changes in the channel characteristics are common. for example if a phone is removed from a wall socket during transmission, the attenuation characteristics of the channel are greatly affected. additionally, the polling algorithm feature of the jackrabbit tm allows random entry by additional stations as in the case of a laptop plugging into a wall jack to use a remote networked printer. the CPC6000 and cpc6100 chipset and associated mac software driver therefore provides automatic speed negotiation from homepna interoperable 0.7mbps up a turbo mode of 10mbs without any user intervention. access id sync interval ethernet data dest. 6 bytes source 6 bytes length 2 crc 4 fixed 15.05 us silence access id symbol 1 sync symbol 0 01 aid blanking interval 11 aid blanking interval access id symbol 2 10 aid blanking interval access id symbol 3 example access id of 00101101 and control word 0001 access id symbol 7 32 bits pcom data symbols ethernet packet 1m8 phy header 129 tics 129 tics 129 tics 129 tics 129 tics 60 tics 20 tics pulse aid blanking interval access id symbol 4 00 129 tics potential pulse position 30.75usec @1 mb/s fixed 120.39 usec 151.14 usec @1 mb/s 1m8 header 1 tic = 116.6667 nsec pcom 4 bytes 66 silence interval = receiver blanking interval access id interval aid blanking interval access id symbol 5 01 129 tics aid blanking interval access id symbol 6 00 129 tics ethernet packet 2 data train. symbol. end of packet non data symbol aid0 aid1 aid2 aid3 aid4 aid5 aid6 aid7 (version) (power) (speed) (reserved) ctrl0 ctrl1 ctrl2 ctrl3 figure 4. homepna 1mb/s frame structure
12 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary phy core description overview in both homepna interoperability mode (1mbps) and high speed turbo mode (10mbps) mode, the jackrabbit tm phoneline chipset along with an ethernet mac essentially perform the same function as a typical ethernet mac/phy nic configuration with only a slight modification to the host based ndis driver for rate adaptation functions. the reason standard ethernet phys cannot be connected to standard twisted pair wire is that those devices require a tightly controlled termination whereby reflected emissions are reduced to a minimum. the home phoneline wire network is exactly the opposite situation where terminations are multiple and incalculable as to the effect on any particular signal. the phy design goal is therefore to get a signal through a multitude of channel types as efficiently as possible. the jackrabbit tm chipset accomplishes this goal as it overcomes the difficulties of the phoneline network through advanced dscm* modulation and atcd* demodulation technologies. the CPC6000 utilizes these new technologies in both the high speed turbo (10mbps) mode of operation and the homepna interoperability (1mbps) mode of operation so that reuse of the chips architecture is maximized. there are parallel front-end pulse detectors that are required to be working at the same time to determine which type of waveform has been received and transmitted. these receivers send data to the mii interface registers so that the host software can build its speed- address look up tables correctly as further described below. a scrambler is also used to randomize the data pattern so that voltage skews cannot be built up on the wire pairs. the maximum voltage output to the twisted pair is below the fcc authorized limit of 560mv. a simplified block diagram of the modem is shown in figure 5, and the afe is shown in figure 6 below. figure 5. simplified CPC6000 phy block diagram tx state machine byte chg encoder data shift logic turbo mode output turbo mode output carrier out carrier in mii parallel to serial scrambler/ descrambler mii registers rom - tx coeff. lut, rx templ. match, tables - turbo & hpna state registers rx state machine byte chg decoder corel./ decision rng pll carrier detect polarity detect collison detect turbo mode input hpna mode input mii 18 to / from cpc6100
13 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary p_comp0 g_comp0 n_comp0 p_comp1 g_comp1 n_comp1 dac_clk dac_[0:7] i ref v ref v_out+ v_out- c_byp p_ref0 sig_in0 g_ref0 n_ref0 p_ref1 sig_in1 g_ref1 n_ref1 8 b i t d a c figure 6. simplified cpc6100 afe block diagram mac interface the interface to the mac is shown in figure 5. in the case of the mii interface, data is received in nibble wide blocks and feeds a parallel to serial conversion process before entering the transmit scrambler. the gpsi interface is inherently serial in nature, and bypasses the parallel to serial conversion process before entering the transmit scrambler. the scrambler itself uses a 2 11 - 1 polynomial to scramble the incoming data. the exact reverse process takes place when receiving data from the demodulator block. the transmit control block sends speed information to the core modulator after receiving that information from either the mii management port or 4-wire serial management interface that is host based driver directed. in the receive direction, the modem core will send the sampling clock to the receive control block. this clock is used to transmit data over either the mii or gpsi interface to the mac. therefore, in the receive direction, data speed will be directed by the receive clock rate over the interface. the receive control block also inputs pulses from both the carrier sense and collision detect logic and relays that to the output pins directly. turbo mode data transmitter scrambled data is passed from the mii/gpsi interface block to the transmit state machine logic. this logic strips the first 64 bits off of the standard ethernet frame, which includes both the preamble and sfd (start of frame delimiter). these bits are replaced with a dcsm preamble as defined below in figure 7. because of this, the dcsm preamble is not scrambled when sent over the twisted pair medium, but has been carefully selected to fit a pseudo-random sequence. preamble (7) delimiter (1) dest addr. (6) scr addr (6) len (2) ethernet data crc (4) synchronization (2) 0011 0011 0011 0011 load temp. (1) 1000 1101 settling time (1) silence period (1) rem. ethernet preamble (3) xxxx xxxx xxxx xxxx xxxx xxxx figure 7. turbo mode preamble
14 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary the preamble shown above allows for synchronization between the transmitter and other receivers on the network, correlator template loading, and an 8 bit settling period followed by an 8 bit silence period. the settling and silence period is used to determine if collisions have occurred on the network over the maximum length of twisted pair wire. the remaining 24 bits of preamble are used for warming up the transmitter, turning on the data valid signal, and sending serial data out. essentially this represents a setup time to present the data to the rll encoder in the case of homepna interoperability (1mbps) mode transmissions or to the phase accumulator in the case of turbo mode (10mbps) transmissions. the remainder of the transmitter is the actual modulator that transforms the scrambled bit stream into symbols. this is the phase accumulator state machine logic that decides which value is output from the dac to the twisted pair wire. these coefficients are cosine segments that represent the magnitude from a maximum to a minimum slope point on a sinusoidal wave pattern. these coefficients are actually an address into a static lut holding binary values to be sent directly into the dac. the phase accumulator also holds a comparator that notifies the state machine if a zero slope point has been reached which indicates the bit edge. the resultant output waveform is precise, requiring only a filter for cleaning dac noise effects on its output. the remaining blocks of the turbo mode (10mbps) transmitter portion of the modem are shown in figure 8 below. homepna interoperability (1mbps) transmitter in homepna interoperability operation, data is passed to the transmit state machine logic in the same fashion as is performed on the high speed turbo mode (10mbps) data stream. the logic will also strip the first 64 bits of the ethernet preamble as specified by the homepna version 1.1 document. the logic attaches the specified homepna 1.1 frame structure as shown in figure 4. therefore, just like turbo mode operation, the preamble is not scrambled. in homepna interoperability mode, however, the 1 mbps transmit frame is passed to an encoder which encodes the data pattern for the time based transmission scheme. the information is then sent to the same coefficient look up table state machine as described in turbo mode for transmission to the dac where the homepna interoperability mode (1mbps) waveform is built. a block diagram of the homepna interoperability mode transmit block is shown below in figure 9. phase accumulator state machine turbo / 10 mbps lut clock driver tx data tx en speed output to d/a packet assembly and transmit control hpna / 1mbps lut id's cntrl's to d/a pcon data in tx_en encoder enable ack req figure 8. post state machine transmitter logic figure 9. homepna 1mbps transmitter logic
15 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary turbo mode receive path there is a limiter circuit that will limit the incoming voltage and magnitude templates as the variance in voltage will be from a minimum of 10mv at the farthest nodes to a 2.5v maximum for a node placed close to the receiver. once data has passed through the comparators, it is presented to a carrier detect mechanism that makes determinations based on the three input slice thresholds and the digital input level. the receiver is polarity insensitive and can determine both positive and negative pulses coming in. this is performed in the carrier detect and polarity detect logic and is done on a continuing basis while the receiver synchronizes on the first 24 bits of known preamble. the receiver will lock within the first 16 bits, but may require up to 24 on severely impaired channels. when the receiver is locked (or framed-up), it begins to load templates that will hold the incoming data stream. this is done with a known data pattern so that known binary levels with channel impairment conditions are stored in the reference templates. future bit values are shifted into registers, compared to the reference templates, and sent to a majority voting state machine. because the bits (grouped 3 at a time) are shifted exhaustedly, high correlation values are scored for the voting process. this is done in parallel with a correlation process on the raw data stream, so that two different scoring methods are engaged to produce the final data stream robustly. the output from the majority voting logic is the data recovered from the input symbol pattern. note that each symbol is over-sampled either 8 or 16 times so that the final score summation of the 8/16 template matching scores for greater accuracy in determining the bit value. this data stream is then fed to state machine logic that strips the first 64bits of the frame and attaches the ethernet preamble and delimiter before being sent to the 2 11 C 1 descrambler in the mii interface (see figures 5 and 6). a block diagram of the turbo mode (10mbps) receiver is shown below in figure 10. carrier detect correlation sync template load collision detect template scoring highest score majority vote 36 chip comparison 64-bit preamble 0011001100110011 10001101 data in 3-bit sr 0 0 0 0 0 0 0 0 1 enable clk out data out col. det car. det 6 6 6 6 6 6 6 figure 10. turbo mode receiver
16 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary homepna interoperability (1mbps) receiver the front end of the receiver for homepna interoperability (1mbps) mode operates completely in parallel with the turbo mode (10mbps) receiver. therefore, upper layer software can have information about which receiver is active so that no latency needs to be built into the receive path even though most of the circuitry is redundant. the homepna 1.1 specification calls for an energy detect voltage threshold slicer for determining the presence of a valid pulse. the jackrabbit tm chipset implements additional decision state logic to improve the 1mbps receiver robustness beyond the specification by correlating total energy over the pulse wave. each pulse is over-sampled by 8x or 16x that provides more consistent detection of timer tic locations. these timer tic locations are related to the actual data stream as shown in figure 4. note that the same carrier sense and polarity detect circuitry is active during homepna interoperability mode reception as in turbo mode (10mbps) and eventually only one of the two receivers will remain active. in fact, the turbo mode (10mbps) receiver will lock onto the data pattern well before the second tic of a homepna 1mbps frame has been decoded as it will lock within 16bt or bit times. by the time a homepna 1mbps receiver begins to receive valid aid symbols, the 10mbps turbo mode receiver will have turned off. the homepna 1mbps receiver will then send the resultant data stream into the rll25 decode state machine logic before the data is then sent to the main receive state machine logic to strip the homepna 1mbps header and attach a standard ethernet preamble and frame delimiter. this state machine then feeds the 2 11 C 1 descrambler within the mii or gpsi interface. a block diagram of the homepna interoperability mode receiver is shown below in figure 11. symbol energy detector data in state machine channel history detector symbol data packet assemby sm rx data rx_clk rx en carrier sense and polarity detect dcsm pulse figure 11. homepna interoperability (1mbps) pulse detector
17 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary interfaces mii interface tx_d0:tx_d3, rx_d0:rx_d3, tx_en, tx_clk, tx_er, rx_dv, rx_clk, rx_er, col, crs, mdc, mdio, md_add0:md_add4 the mii interface implemented in the CPC6000 device is compatible with the ieee 802.3u specification, and constitutes 18 pins. in that specification, mii interface registers are defined such that the first 16 registers must have defined or reserved values in them. these registers constitute the basic and part of the enhanced register set. registers 16 C 32 are defined as extended and vendor specific by the ieee. note that registers 2 and 3 expect to be filled in with the oui (organizationally unique identifier, which for cp clare is 0x00-30- 15), the manufacturers model number, and the revision number. this allows the host software (ndis driver) the option of booting with vendor specific code that can drive the vendor specific registers correctly. the CPC6000 uses this vendor specific register area to manage the interaction between a standard 802.3 mac and the phoneline phy. as per the 802.3u specification, these registers are read and written to over the mii management interface, which has its protocol, pins, and timing, specified. the registers are updated by data transmitted on the mdio pin and clocked in and out of the registers by the mdc pin. the registers and definitions are defined in the following section. on boot-up, the system software driver will poll the status of the md_add0:md_add4 pins to determine the mii hardware address. the 802.3 specification allows for 32 independent devices to be attached to the mac any one of which can be operational at one time. the user can use pull up or pull down resistors externally to force the appropriate address desired to be read by the mac. register 0 C control register this is a basic register that must be included in every mii interface. the register is set for 100 mb/s operation, and defaults by tri-stating the mii interface at boot-up. bits 9, 8, 6, 5, 4, 3, 2 and 1 are ignored by the CPC6000 phy. bit # def aul t name description type 15 0 reset sets phy in reset state rw/sc 14 0 loopback loopback disabled rw 13 1 speed select combined with bit 6 rw 12 0 auto-negotiate 0 = disable auto-negotiation rw 11 0 power down 1 = enable power down rw 10 1 isolate 1 = electrically isolate phy from mii rw 9 0 restart auto-neg 1 = restart, 0 = normal operation rw/sc 8 0 duplex mode set in half duplex mode rw 7 0 col test 1 = enable col signal test rw 6 0 speed select msb. sets phy in 100mb/s mode rw [5:0] 0 reserved write as 0 rw mii vendor specific register definitions note - the type field has the following meanings: rw = read/write bit rw/sc = read/write self clearing ro = read only ro/ll = read only latch low, cleared on read ro/lh = read only latch high, cleared on read
18 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary register 1 C status register this is also a basic register and must be included with every mii interface. bits 6, 5, 4, 3 and 1 are ignored by the CPC6000 p hy. bit # def aul t name description type 15 0 100 baset4 set to unable to perform 100baset4 ro 14 0 100basex fd set to unable to perform 100basex full duplex ro 13 0 100basex hd set to unable to perform 100basex half duplex ro 12 0 10mb/s fd set to unable to perform 10mb/s full duplex ro 11 1 10mb/s hd set to able to perform 10mb/s half duplex ro 10 0 100baset2 fd set to unable to perform 100baset2 full duplex ro 9 0 100baset2 hd set to unable to perform 100baset2 half duplex ro 8 0 extended status no extended status in register 15 ro 7 0 ignore ignore this when read ro 6 0 mf preamble set to force management frames with preamble ro 5 0 auto-neg complete set to auto-negotiation not complete/not capable ro 4 0 remote fault default is no remote fault condition detected ro/lh 3 0 auto-negotiate set to unable to auto-negotiate ro 2 1 link status default is set to link status up ro/ll 1 0 jabber detect set to no jabber condition detected ro/lh 0 1 extended registers set to use upper 16 registers for jackrabbit? ro register 2 C phy identifier register this register contains bits 3 to 18 of the organizationally unique identifier, where bit 3 of the oui is mapped to the msb of r egister 2. this register is hard-wired and read only. bit # def aul t name description type [15:0] 0000 0000 0011 0010 oui oui is mapped per ieee specification ro register 3 C phy identifier register this register holds the remaining bits of the oui (bits 19 to 24, with bit 19 of the oui mapped to the msb of register 3), the manufacturers model number, and the revision number. bit # def aul t name description type [15:10] 10 1000 oui upper 6 bits of the oui ro [9:4] 00 0000 mfr. model # read cp clare model number ro [3:0] 0 mfr. rev. # read cp clare revision number ro registers 4 C 8: auto-negotiation registers these registers will be set to all 0s since auto-negotiation is turned off since it has no meaning in phoneline phy silicon. these are read only as they are never used and should not be changed. bit # def aul t name description type [15:0] 0000 0000 0000 0000 auto-neg. regs. auto-negotiation registers ro
19 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary registers 9 & 10: 100 baset2 control and status registers the 100 baset2 control register is a ro register with defaults at 0. this will be set to all 0s. the status register is ro, and will be set to all 0s. bit # def aul t name description type [15:0] 0000 0000 0000 0000 100baset2 100baset2 control and status registers ro registers 11 to 14: reserved registers these registers are reserved by the ieee, and are all set to 0s and are read only. bit # def aul t name description type [15:0] 0000 0000 0000 0000 reserved reserved by the ieee ro register 15 C extended status register this register is implemented only for phys capable of speeds over 100mb/s, and as such, will be set to all 0s and be read onl y. bit # def aul t name description type [15:0] 0000 0000 0000 0000 ext. status used for 1gb/s lans status ro register 16 - CPC6000 phy control register this register prevents non-jackrabbit tm phy aware macs from inadvertently writing into the jackrabbit tm phy specific registers. bit # def aul t name description type 10 0 reserved bit reserved for future use r/w 9 0 turbo status turbo link status. 1=turbo packet detached r/w 8 1 1m8 sense identifies 1m8 packet source. 0=legacy detect only r/w 41 2 0 legacy 1m8 set if legacy 1m8 source detected. invalid if bit 8=0 r/w 1 0 CPC6000 1m8 set if CPC6000 1m8 source detected. invalid if bit 8=0 r/w registers 17 C 23: unused registers these registers are not being used by the CPC6000 phy, and will be read back as all 0s. bit # def aul t name description type [15:0] 0000 0000 0000 0000 unused unused registers ro
20 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary register 24: CPC6000 clock control register the register is used to set the internal clock registers. bit # def aul t name description type [15:13] 101 reserved reserved for phy [12:9] 1 110 pll 60 count sets pll counter for 60mhz internal clock r/w 8 0 reserved reserved r/w 7 0 forced turbo sets phy to turbo mode only. 1=forced turbo r/w 6 0 forced 1m8 sets phy to 1m8 mode only. 1=forced 1m8 r/w 5 0 reserved reserved for phy [4:0] 1 1111 pll 80 count sets pll counter for 80mhz internal clock r/w register 25-26: CPC6000 phy scratch pad registers these registers are used internally by the phy. do not read or write to these registers. a read to these registers will return undefined values. bit # def aul t name description type [15:0] random-undetermined reserved reserved for phy ro registers 27 C 29: unused registers these registers are not being used by the CPC6000 phy, and will be read back as all 0s. bit # def aul t name description type [15:0] 0000 0000 0000 0000 unused unused registers ro register 30: user data channel bit # def aul t name description type [15:12] random reserved bit reserved for future use ro [11:10] 11 turbo speed rx packet speed. 11=10mbps, 10=5mbps, ro 01=2mbps, 00=1mbps 9 0 1m8 packet rx 1m8 packet ro 8 0 new data set to 1 if user data is new since last read ro [7:0] random user data user data byte. remains valid until register is read ro 9 0 data enable enable for interrupt on new user data wo [7:0] random user data sets new bit on receiving phy when written wo register 31: r16 alias this register uses the lower bits as an alias to register 16 for programming convenience, other bits are unused and should be r ead as 0s. bit # def aul t name description type [15:4] 0000 0000 0000 unused unused registers ro [3:0] r16 [15:12] r16 alias alias for register 16 bits [15:12] ro the mii interface receives nibble wide data from an industry standard 802.3 mac, performs parallel to serial conversion, and shifts the data into a transmit scrambler. the data is clocked in on the rising edge of tx_clk when tx_en is enabled (driven high) on the first nibble of the preamble. there is no buffering of data between the mii and scrambler so that no measurable delay is inserted into the transmission path.
21 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary tx block spi rx block txd0 tx_en tx clk spi_dout rxd0 rx clk crs col serial flow serial flow mii registers 0: control 1: status 2,3: phy identifier 4-7: auto negotiate 8-15: reserved 16-31: vendor transmit scrambler tx control receive descrambler mii alignment rx control tx data speed tx_en tx clk rx data rx clk rx_dv clsn crs spi_din spi_cs spi_clk figure 12. mii interface block diagram seven wire serial (gpsi) interface note: the gpsi interface mode will not be active in first version (CPC6000a) silicon. tx_d0, rx_d0, tx_en, tx_clk, rx_clk, col, crs, gpsi_en typically used as the digital interface in a usb mac or a pcmcia mac application, the gpsi interface is an industry standard 7-wire interface used in many 10baset ethernet designs. the seven signals (tx_d0, rx_d0, tx_en, tx_clk, rx_clk, col, and crs) that comprise the gpsi interface also serve the same function in the mii interface. the major difference between this interface and the mii interface is that the tx_clk and rx_clk are continuous in mii mode, but are gapped in gpsi mode. the gpsi interface is enabled in the phy by holding the gpsi_en pin low during the reset pulse. table 1 C gpsi interface signals s i gnal description tx_clk transmit clock tx_en transmit enable tx_do transmit data rx_clk receive clock rx_do receive data crs receive carrier sense col collision (active high) the mii also transmits nibbles received from the descrambler to an industry standard 802.3 mac by performing serial to parallel conversion on a nibble of data. the data is clocked out on the rising edge of rx_clk when rx_en is enabled (driven high) beginning with the sfd (start of frame delimiter). in the present implementation, neither tx_er nor rx_er is connected to any logic inside the CPC6000. collision detect is determined and the col signal is asserted if a collision is detected on the twisted wire medium during the silence period of the ethernet preamble (see fig 4 for the homepna version 1.1 silence period). back-off timing is determined by the 802.3 standard beb algorithm. carrier sense is asserted when either the transmit or the receive silicon blocks are active. as per the homepna version 1.1 specification, carrier will be asserted within 815ns after the detection of a valid pulse. it will also be turned off after the receiver has sensed no voltage above the squelch limit for 29.8us (if it has been 120us since carrier asserted), or 16us if longer than 120us since carrier asserted. in turbo mode, the crs is turned off 2bt (bit times) after the conclusion of the frame reception. a block diagram of the mii interface is shown in figure 12 .
22 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary serial peripheral interface spi_di/mdio, spi_dout, spi_clk/mdc, spi_cs this is a simple 4-trace interface C spi_din, spi_dout, spi_cs, and spi_clk. this interface is used in conjunction with the gpsi port to commute speed change information to the modulator from the mac. since there are neither registers nor any management interface, the spi port acts like an mii management interface when used with a gpsi port. this port is double buffered and serial so that as data is shifted in serially on the rising edge of spi_clk, it is also shifted in parallel into the second buffer when spi_cs goes high. in effect, spi_cs acts like a load strobe to shift data from the serial buffer into the parallel buffer. figure 13 shows the second-generation phy silicon (CPC6000b) to mac interface when configured in gpsi mode (and thereby also configuring the spi interface). tx block spi rx block txd0 tx_en tx clk spi_dout spi_din rxd0 rx clk crs col serial flow serial flow mii registers 0: control 1: status 2,3: phy identifier 4-7: auto negotiate 8-15: reserved 16-31: vendor transmit scrambler tx control receive descrambler mii alignment rx control tx data speed tx_en tx clk rx data rx clk rx_dv clsn crs spi_cs spi_clk figure 13. gpsi and spi port interfaces comparator (adc) interface n_comp, g_comp, p_comp pins, manch_clk these pins connect the demodulator inside the modem to comparators inside the afe. the pins ending with 1 are those in the main receive path from the twisted pair wire for homepna transmissions. the second set, those ending with a 2, are used to receive transmissions from an ethernet nic card in the dongle mode from a second set of comparators inside the afe. in this dongle mode, transmissions received from the ethernet nic are demodulated through the endec and routed through the CPC6000 modulator for the dac to twisted pair wire in the transmit path. conversely, signals received from the twisted pair wire are received through the 1 set of comparators, demodulated, and sent through the manchester transmit pins (manch_p, manch_n) to the ethernet nic card. the voltages on these wires are compatible with either 3.3v or 5v interface logic. these traces are directly connected between the two chips, and no external components are required (pull-ups, etc.). the sampling rate on comparator set number 1 is driven by the dac_clk, and the second set of comparators is clocked by the manch_clk pin on the 80 pin device. n_ref1,2 g_ref1,2 pref1,2 sig_in1,2 these are analog inputs to the afe comparators from the twisted pair wire. all inputs ending with a 2 are inputs from an ethernet nic card for use in a dongle application previously described where one end communicates with an ethernet nic card and the other with standard twisted pair wire. all inputs ending with a 1 are directly connected
23 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary with the twisted pair wire. the n_ref, g_ref, and p_ref signals are connected to the inverting end of the comparator, and the sig_in signal represents the input from the wire through an anti-aliasing filter. all of the positive inputs to the comparators are connected to the sig_in trace. dac interface dac0:dac7, dac_clk, dac_scal these pins directly connect the modulator and 8 bit dac inside the afe. these traces require no external discrete devices between chips such as pull-ups, etc. inside the afe, digital inputs are latched on the rising edge of dac_clk, which drives the update rate up to 125ms/s. dac_clk is an output from the modem and is either directly connected through the modem to the modems input clock, or is fed from a divided down modem clock. the data inputs are compatible with either 3.3v or 5v logic. the dac_scal output from the modem to the afe determines which set of coefficients to use from the internal lut to be sent to the dac so as to adjust the drive current for either hpna interoperability or turbo mode operation. this is accomplished by setting the bias inside the afe through a fet which switches in a resistor in parallel thereby setting the reference voltage inside the afe. i_pos, i_neg these signals represent a differential analog output signal and are directly connected from the dac output on the afe to a center-tapped transformer through a bandpass filter and an amplifier. these are current outputs, and can be adjusted from 2ma to 10ma which represents the full swing output without any degradation of signal quality. an external drive circuit is all that is required to connect to the twisted pair wire. the output capacitance is less than 5pf. ethernet nic dongle interface note: the dongle interface will not be active in first generation (CPC6000a) silicon. manch_p and manch_n these pins are capacitively coupled to an aui transformer on an industry standard 802.3 compliant ethernet nic card. these pins provide a manchester encoded pulse that emulates the analog pulses required for connection to a rx+ and rx- connection from a twisted pair wire to a standard nic card. as described above, the flow of this data connection is actually from the twister pair through the comp2 section of the afe (see the comparator section above), through the demodulator circuit in the digital chip, and then out the manch_p and manch_n pins to the nic card. the voltage swing on these pins is from (tbd)v to (tbd)v. clocks input clock options option 1: clk_in_80, clk_in_60 signals these signals are inputs from standard crystal oscillators that provide the master clock to both the CPC6000 digital phy and cpc6100 afe. they provide the sampling rate on the dac for data transmission and the oversampling rate in the modem. a .1uf bypass capacitor is connected between the oe and gnd pins of the oscillator. in addition, a 10-ohm resistor is placed in series between the vcc pin and the +5v power plane. the output of the oscillator is connected directly to the clock inputs. the tolerance on the oscillators shall be +/- 50ppm with an allowable jitter of <1ns max. option 2: xtal1, xtal2, pll_80_lf2, pll_60_lf2: these are the inputs for the 25mhz crystal that drives the internal plls incorporated in the CPC6000. the crystal shall be of fundamental frequency with a tolerance of +/- 50ppm. the pll will be connected to an external filter for each frequency (80mhz and 60mhz) and then connected to digital ground. the internal pll will output the fundamental clocks for all internal functions with the 80mhz clock driving all turbo mode (10mbps) operations and the 60mhz clock used for all homepna interoperability (1mbps) operations. output clock ck_25 this is a 25mhz output clock used to drive the mac so that no external clocking source is required for that device. this clock will also have a tolerance of +/-50ppm with an allowable jitter of <1ns. pins for device testing test_xmit1, test_xmit10, ck_60_mon these pins are used to test the silicon. they should be treated as a no connect and left floating. essentially, the pins will force either homepna interoperability mode or 10mbps turbo mode only; not both or either. miscellaneous pins leds: link_act, rx_mode: the link_act pin will output a 16ma source current to drive an led when the link is considered active; if there has been receive activity within the last 4 seconds. the rx_mode pin will be an indicator for the mode of operation (homepna interoperability or turbo) chip is currently operating. it
24 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary will source a 16ma current if the chip is operating in turbo mode. inta pin this pin provides a standard logic signal from the CPC6000 to signal the host to read both the mii status register and the jackrabbit tm status register. this is provided for software drivers that would prefer an interrupt driven mii interface rather than a standard 802.3 polled interface. if this pin is not connected, it should be left floating as a nc signal. reset pin this pin, when activated, will reset the CPC6000 device and return all mii register settings to their default state. this pin is active high, and should have a pull down resistor on the trace for normal operation. pulling the pin high for a period of (tbd)ms will activate the reset signal. note that reset of the device can also be effectuated by the host software driver. a 0 is written to bit 15 in the mii control register to begin the reset process. rref: this pin is used for setting a reference for the pll incorporated in the CPC6000 and should be tied through a 6.19k resistor to digital ground. r_bias this pin is used to set a reference inside the cpc6100 afe and should be tied through a 4k resistor to digital ground. note that this pin is also connected through a fet in parallel through another 4k resistor to the dac_scal pin on the CPC6000 digital phy. rb/dd this pin acts as a voltage divider inside the cpc6100 afe and should be connected through a 2k resistor to digital power. phoneline interface external components line driver the line driver is a high speed voltage feedback amplifier with 160mhz bandwidth and 160v/us slew rate for fast settling time and high speed data transfer rates that peak at 10mb/s. it is capable of driving 50ma from a single +5v supply. it takes a differential signal from the dac and outputs a single trace output to the transformer. the driver provides > -85db of harmonic distortion at 1mhz. receive path the receive path contains an active/passive bandpass 4-pole filter with amplifiers that provide (tbd)db of gain to the incoming signal. the gained signal is further sent to a limiting section which soft-limits the signal to +/- 500mv max through 5ghz transistors. the limiting section also provides a further gain of (tbd)db. this provides enough of a gain to correlate 10mvp signals as well as limit 2.5v signals from closely spaced homepna 1mbps nodes so as not to saturate the receiver section. isolation this is a 1:1 ferrite transformer that provides 1500vrms of isolation from line transients or power crosses that might occur due to the fact that home telephone wires are connected directly to the pstn. the signal rise time is 3.5ns maximum, and the leakage inductance is less than .2uh. in addition, the dcr is .20ohms max, and the inductance at 100khz and .01vrms is 100uh. transmit filter a fourth order bandpass filter is utilized to pass jackrabbit tm standard frequencies while removing noise and other carrier frequencies from interfering with the demodulation process. the output of the filter is a 5.5mhz to 24.5mhz frequency band that is sent to the line driver. front end protection the circuitry from the transformer to the twisted pair wire is known as the front-end circuitry. since it is connected in parallel with pots telephone service, protection must be provided from central office supervisory signaling such as ringing. therefore, two .001uf, 250v dc blocking capacitors are required as well as two ferrite beads and a sidactor for voltage surges such as lightening strikes. these discrete devices are typically found on most voice band modems for the same reasons as those mentioned above.
25 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary electrical characteristics operating conditions (CPC6000 and cpc6100) maximum guaranteed ratings: operating temperature: 0c C 70c storage temperature: -40c C 125c soldering temperature: 225c for 10sec. positive voltage on any pin: vdd +.5v negative voltage on any pin: vdd - .5v maximum: vdd: 7v CPC6000 dc electrical characteristics ( ta = 0c C 70c, vdd = 3.3v +/- 5%) CPC6000 ac electrical characteristics ( ta = 0c C 70c, vdd = 3.3v +/- 5%) characteristic symbol min typ max units conditions clk_in_80 +/- 50ppm mhz duty cycle 40 60 % clk_in_60 +/- 50ppm mhz duty cycle 40 60 % rx_clk tx_clk mdc characteristic symbol min typ max units conditions input voltage level high vih vdd-.75 vdd+.75 v voltage level low vil 0 0.75 v current level high iih 5 ua current level low iil -5 ua no pull up pin cap to gnd 10 pf includes package output voltage level high voh vdd-.5 vdd+.5 v -7ma voltage level low vol 0 0.5 v +7ma current level high ioh - measured on afe current level low iol - measured on afe rise time 4 ns .4v to 2.5v into 20pf load fall time 4 ns 2.5v to .4v into 20pf load pin cap to gnd 10 pf supply current homepna mode active tbd ma suspect below 100ma turbo mode active tbd ma low power mode tbd ma
26 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary cpc6100 dc electrical characteristics (ta = 25decc, vdd = 3.3v +/-5%) characteristic symbol min typ max units conditions input (digital) voltage level high vih vdd-.4 vss+.4 v voltage level low vil vss 0.75 v current level high iih 5 ua current level low iil -5 ua no pull up pin cap to gnd 10 pf includes package output(digital) voltage level high voh vdd-.6 vss+.6 v -7ma voltage level low vol 0 0.5 v +7ma current level high ioh - measured on afe current level low iol 5 measured on afe rise time 5 ns .4v to 2.5v into 20pf load fall time 5 ns 2.5v to .4v into 20pf load pin cap to gnd 10 pf input(analog) voltage range: p_ref 0 0.5 v g_ref 0 0.4 v n_ref -0.4 0 v sig_in -0.5 0.5 v output(analog) voltage range: 20 ma v_out+, v_out- -1 1.25 v current source driver, but max voltage compliance supply current homepna active 55 ma turbo active 60 ma low power mode 36 ma propagation delay transmit delay 10 ns receive delay 20 ns dac specs. resolution 8 bits monotonicity guaranteed guaranteed integral linearity error -1 1 lsb differential nonlinearity -1 1 lsb offset error -0.01 0.01 %fsr gain error -10 10 %fsr full scale output current 10 ma output resistance 100 k w output capacitance tbd pf internal vref 1.15 1.29 v internal rref 11 65 k w offset drift tbd ppm gain drift tbd ppm comparator specs. input offset voltage +/-25 mv input capacitance 10 pf min overdrive v 50 mv
27 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary cpc6100 ac electricalspecifications characteristic symbol min typ max units conditions dac characteristics max update rate 80 ms/s maximum rate output settling time tbd ns looking for under 35ns for full s glitch impulse tbd pv-s looking for max 5 output rise time 1 ns output fall time tbd ns looking for >-50 all conditions sndr tbd db looking for >-60 all conditions thd tbd dbc looking for >60 all conditions dynamic range tbd dbc comparator specifications max input sig freq 15 mhz propagation delay tbd ns looking for <23ns max output update rate 80 ms/s
28 jackrabbit tm CPC6000/cpc6100 preliminary specifications rev. 0a, 3/13/00 preliminary mechanical dimensions CPC6000 phy cpc6100 afe 40 21 0,13 nom 0,25 0,75 0,45 seating plane 0,05 min gage plane 0,27 41 0,17 20 60 1 61 80 sq sq 12,20 13,80 14,20 11,80 9,50 typ 1,05 1,20 max 0,95 0,08 0,50 m 0,08 05 75 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026, variation add gage plane 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 0,17 0,27 24 25 13 12 sq 36 37 7,20 6,80 48 1 5,50 typ sq 8,80 9,20 1,05 0,95 1,20 max 0,08 0,50 m 0,08 05 75 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026, variation abc
asia pacific asian sales office clare room n1016, chia-hsin, bldg ii, 10f, no. 96, sec. 2 chung shan north road taipei, taiwan r.o.c. tel: 886-2-2523-6368 fax: 886-2-2523-6369 japan japanese sales office clare tosei building 5f 2-23-1, ikebukuro, toshima-ku tokyo 171 tel: 03-3980-2212 fax: 03-3980-2213 headquarters clare 78 cherry hill drive beverly, ma 01915 tel: 1-978-524-6700 fax: 1-978-524-4900 toll free: 1-800-272-5273 http://www.cpclare.com clare makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are non-infringing on any valid us or foreign patents. cp clare assumes no liability as a result of the use of said specifications and re- serves the right to make changes to specifi- cations without notice. cp clare does not au- thorize or warrant any cp clare device for use in life support devices and/or systems. con- tact your nearest cp clare sales office for the latest specifications. worldwide sales offices north america north american sales office clare 78 cherry hill drive beverly, ma 01915 tel: 1-978-524-6700 fax: 1-978-524-4900 toll free: 1-800-272-5273 eastern regional sales clare 78 cherry hill drive beverly, ma 01915 tel: 1-978-524-6700 fax: 1-978-524-4900 toll free: 1-800-272-5273 mid-american regional sales clare 78 cherry hill drive beverly, ma 01915 tel: 1-978-524-6700 fax: 1-978-524-4900 toll free: 1-800-272-5273 northwestern regional sales clare 2010 crow canyon place suite 100 san ramon, ca 94583 tel: 1-925-277-3422 fax: 1-925-277-3423 toll free: 1-800-272-5273 southwestern regional sales clare 2816 nevis circle costa mesa, ca 92626 tel: 1-714-556-3661 fax: 1-714-546-4254 toll free: 1-800-272-5273 canadian regional sales clare canada ltd. 3425 harvester road suite 202 burlington, ontario l7n 3n1 tel: 1-905-333-9066 fax: 1-905-333-1824 europe european sales office cp clare nv bampslaan 17 b-3500 hasselt (belgium) tel: 32-11-300868 fax: 32-11-300890 france cp clare france 31 cours des juilliottes 94700 maisons alfort france tel: 33 (0) 1-56-29-14-14 fax: 33 (0) 1-56-29-14-15 germany cp clare elektronik gmbh leonberger strasse 20 d-71638, ludwigsburg tel: 49-7141-9543-0 fax: 49-7141-9543-20 italy c.l.a.r.e.s.a.s. via c. colombo 10/a i-20066 melzo (milano) tel: 39-02-95737160 fax: 39-02-95738829 sweden clare sales comptronic ab box 167 s-16329 sp?nga tel: 46-862-10370 fax: 46-862-10371 united kingdom clare uk sales marco polo house cook way bindon road taunton uk-somerset ta2 6bg tel: 44-1-823 352541 fax: 44-1-823 352797 specification: ds-CPC6000/cpc6100-r0a ? copyright 2000, cp clare corporation d/b/a clare all rights reserved. printed in usa. 3/13/00 * jackrabbit ? utilizes cosine segment modulation (csm), dual carrier segment modulation (dcsm) and adaptive template demodulation (atcd) which are patent and patent pending technologies of x-com inc., mannasses, va, usa

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